Rating:
(4 reviews)
Author: Rakesh Chadha
ISBN : 1441947159
New from $177.79
Format: PDF
Direct download links available Static Timing Analysis for Nanometer Designs: A Practical Approach [Paperback] Free Download for everyone book with Mediafire Link Download Link
The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.
The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.
This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.
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- Paperback: 572 pages
- Publisher: Springer; 2009 edition (February 28, 2014)
- Language: English
- ISBN-10: 1441947159
- ISBN-13: 978-1441947154
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Static Timing Analysis for Nanometer Designs: A Practical Approach Free Download
I'm disappointed with "Static Timing Analysis for Nanometer Designs"
by Bhasker and Chadha, a very expensive book that explains the basics
about static timing analysis, illustrated using a specific tool,
PrimeTime from Synopsys, Inc.
There's little to nothing about how timing analysis itself is done;
for that, try "Timing", by Sachin Sapapnekar. The focus in Bhasker
and Chadha is on constraint modeling, illustrated with the modeling
language SDC, Synopsys Design Constraints.
The physical book is well made and with good quality paper and print.
It is easy on the eyes -- there's lots of white space and timing
diagrams and basic examples, and no obvious typos. And lots and lots
of timing output reports, so many than one's eyes tend to glaze over,
but good to have when you need them. But in too many cases, the
figures are on different pages from the prose describing them, leading
to a lot of page flipping, which impedes learning.
The book is expensive -- it lists for $209.00, and the best price I
found was Amazon's at $165.87. For that kind of money, I want more
insight, more detail, more value. Yet I often felt like I was reading
a user's manual for a tool.
There is a conflict in exposition between simplicity (explain the
basic idea) and complexity (deal with the general case). I'm not a
timing expert, but for a "book [that] can be used as a reference for a
graduate course in chip design" (p. xivv), the exposition stayed quite
rudimentary. Most explanations are predicated on a common clock, and
some issues with setup and hold on multi-cycle paths are not
mentioned; e.g.
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